verilog 0~9까지 세는 Counter(카운터) 설계하기

module <counter.v>

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/03/06 09:23:28
// Design Name: 
// Module Name: counter
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

//a : clock, b: start, c : o_cout
module counter(
    input a,
    input b,
    output reg[3:0] c
    );
    always@(posedge a) begin
        //start = 1일때 c = 4'b0000초기화
        if(!b) begin
            c<=4'b0000;
        end 
        //clock에 의한실행
        else begin
            if(c == 4'b1001) begin
                c<=4'b0000;
            end
            else begin
                c<=c+4'b0001;
            end
        end
    end
endmodule

 

testbench : <tb_counter.v>

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/03/06 09:27:12
// Design Name: 
// Module Name: tb_counter
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_counter;
    reg clock,start;
    wire [3:0] o_cout;
    
    //module
    counter u1
    (.a(clock),.b(start),.c(o_cout));
        
    initial 
    begin
        clock = 0;
        forever #5 clock = ~clock;
    end
    
    initial
    begin
        #0 start = 0;
        #20 start = 1;
        #300 $finish; // Finish simulation after 100 time units
    end
    
endmodule

 

<결과 파형>